1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, in particular, relates to a semiconductor device that is capable of reduction in thickness and high-density mounting and that is simple in manufacturing process, and further relates to a manufacturing method of such a semiconductor device.
This application is counterpart of Japanese patent application, Serial Number 372734/2002, filed Dec. 24, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, as semiconductor devices capable of high-density mounting, there have been known semiconductor devices of a multi-chip package (hereinafter referred to as “MCP”) structure in which a plurality of semiconductor elements (hereinafter referred to as “chips”) are mounted within one package.
For example, when two chips having chip sizes equal to or approximately equal to each other are stacked in an MCP of a two-chip stacked type, the lower chip is fixed onto a substrate using a bonding material, then a spacer such as a silicon piece or tape is fixed onto the lower chip using a bonding material, and wiring is implemented from the lower chip to bonding posts on the substrate using the wire bonding technique. Then, the upper chip is fixed onto the spacer using a bonding material, and wiring is implemented from the upper chip to the bonding posts on the substrate using the wire bonding technique. Subsequently, the lower chip, the upper chip and the wiring are sealed using resin, and then terminals are attached to the underside of the substrate.
However, there are drawbacks about the foregoing MCP that inasmuch as the spacer is used, a three-chip stacked structure is resulted so that not only the thickness of the whole package is increased, but also assembling steps are increased to raise material cost and assembling cost.
In view of this, as MCP structure semiconductor devices that have solved such drawbacks, there have been proposed those as described, for example, in the following patent literatures 1 and 2.
[Patent Literature 1]                JP-A-2001-94045        
[Patent Literature 2]                JP-A-2002-124625        
In each of the semiconductor devices described in the patent literatures 1 and 2, a substrate is formed with an opening portion leading from its front surface to its back surface, and a lower chip is received in the opening portion with its front surface facing downward. Onto a back surface of the lower chip, for example, a back surface of an upper chip that is the same as or approximately the same as the lower chip is fixed. Wiring is carried out from the upper chip to bonding posts on the front surface of the substrate using the wire bonding technique, and the upper chip and the wiring are sealed with resin. Terminals are provided on the back surface of the substrate and electrically connected to the bonding posts on the front surface thereof via through holes. Accordingly, for electrical connection between the upper chip and the lower chip, wiring is carried out from the lower chip to the terminals on the back surface of the substrate using the wire bonding technique, or the lower chip and the terminals on the back surface of the substrate are connected on the side of an external device.
The foregoing MCP can solve the foregoing drawbacks because the chips having the chip sizes equal to or approximately equal to each other can be stacked in a two-chip fashion without using a spacer.
However, there has been the following problem with respect to the conventional semiconductor devices of the foregoing patent literatures 1 and 2.
When electrically connecting the upper chip and the lower chip to each other, the wiring is carried out from the lower chip to the terminals on the back surface of the substrate using the wire bonding technique, or the lower chip and the terminals on the back surface of the substrate are connected on the side of the external device. Therefore, there has been a problem that the thickness of the whole package is increased by a height of the wiring on the side of the lower chip, or that inasmuch as the lower chip and the terminals on the back surface of the substrate should be electrically connected on the side of the external device, an extra connecting operation is required to deteriorate the convenience of use.